Introduction to VHDL

VHDL is the acronym for Very High Speed Integrated Circuit Hardware Description Laguage.It is a Digital Integrated circuit design tool ,which is widely using now.There are many tools in IC designing that can be used in place of VHDL(Example Verilog).But VHDL is the most poplar HDL among all HDLs now using in industry.Initially VHDL was developed by U.S Department of Defence.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of charactercalled string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended thecharacter type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed andunsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwavecircuit design extensions.

In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was approved by REVCOM in September 2008.

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VHDL MODEL OF 8:1(8 INPUT) MULTIPLEXER

Multiplexer is simply a data selector.It has multiple inputs and one output.Any one of the input line is transferred to output depending on the control signal.This type of operation is usually referred as multiplexing .In 8:1 multiplexer ,there are 8 inputs.Any of these inputs are transferring to output ,which depends on the control signal.For 8 inputs we need ,3 bit wide control signal .

Working:If control signal is "000" ,then the first input is transferring to output line.If control signal is "111",then the last input is transferring to output.Similarly for all values of control signals.A simple block diagram of 8:1 multiplexer is shown here.



Now see the VHDL code of 8:1 multiplexer

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC);
END MUX8_1;
ARCHITECTURE BEH123 OF MUX8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;
END PROCESS;
END BEH123;

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Comparison of VHDL to Other Hardware Description Languages

VHDL Disadvantages

·         VHDL is verbose, complicated and confusing

·         Many different ways of saying the same thing

·         Constructs that have similar purpose have very different syntax (case vs. select)

·         Constructs that have similar syntax have very different semantics (variables vs signals)

·         Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)

VHDL Advantages

·         VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.

·         VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.

·         VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.

·         VHDL has a rich collection of datatypes

·         VHDL is a full-featured language with a good module system (libraries and packages).

·         VHDL has a well-defined standard.

VHDL and Other Languages

·         VHDL vs Verilog

o    Verilog is a "simpler" language: smaller language, simple circuits are easier to write

o    VHDL has more features than Verilog

§  richer set of data types and strong type checking

§  VHDL offers more flexibility and expressivity for constructing large systems.

o    The VHDL Standard is more standard than the Verilog Standard

§  VHDL and Verilog have simulation-based semantics

§  Simulation vendors generally conform to VHDL standard

§  Some Verilog constructs don't simulate the same in different tools

o    VHDL is used more than Verilog in Europe and Japan

o    Verilog is used more than VHDL in North America

o    South-East Asia, India, South America - More Democratic

·         VHDL vs SystemC

o    System C looks like C —familiar syntax

o    C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?

o    If you think VHDL is hard to synthesize, try C....

o    SystemC simulation is slower than advertised

·         VHDL vs Other Hardware Description Languages

o    Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.

o    SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.

o    Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.

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Difference between rising_edge(clk) and (clk'event and clk='1')

Only few VHDL programmers know that there is something called "rising_edge()" function.Even those who know about it, they still stick to the old fashioned clk'event and clk='1' method of finding an edge transition of clock.So in this article I will explain the difference between rising_edge or falling_edge function and clk'event based edge detection.

Consider the following snippet:

clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  --for 0.5 ns 
signal is '0'.
       
clk <= '1';
        wait for clk_period/2;  --for next 0.5 ns 
signal is '1'.
   end process;

process(clk)
begin
if(rising_edge(clk)) then
xr<= not xr;
end if;

if(clk'event and clk='1') then
x0 <= not x0;
end if;

end process;

If you run the above code the output will look like this:

Now you may ask where is the difference? There is no difference in this case.But let us see another example:

clk_process :process
   begin
        clk <= 'Z';    ----------Here is the change('Z' 
instead of '0').
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        clk <= '1';
        wait for clk_period/2;  --for next 0.5 ns 
signal is '1'.
   end process;

process(clk)
begin
if(rising_edge(clk)) then
xr<= not xr;
end if;

if(clk'event and clk='1') then
x0 <= not x0;
end if;

end process;

Now the output will look like this:

Does this ring any bells?You can see that the signal 'xr' doesn't change at all,but x0 changes as in the first code.Well this is the basic difference between both the methods.To get a clear view look at the rising_edge function as implemented in std_logic_1164 library:

    FUNCTION rising_edge  (SIGNAL s : std_ulogic)
    RETURN BOOLEAN IS
    BEGIN
        RETURN (s'EVENT AND (To_X01(s) = '1') AND
                            (To_X01(s'LAST_VALUE) = '0'));
    END;

    As you can see the function returns a value "TRUE" only when the present value is '1' and the last value is '0'.If the past value is something like 'Z','U' etc. then it will return a "FALSE" value.This makes the code, bug free, beacuse the function returns only valid clock transitions,that means '0' to '1'.All the rules and examples said above equally apply tofalling_edge() function also.

But the statement (clk'event and clk='1') results TRUE when the present value is '1' and there is an edge transition in the clk.It doesnt see whether the previous value is '0' or not.



Note :- Use rising_edge() and falling_edge() functions instead of (clk'event and clk='1') statements in your designs.

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