Comparison of VHDL to Other Hardware Description Languages

VHDL Disadvantages

·         VHDL is verbose, complicated and confusing

·         Many different ways of saying the same thing

·         Constructs that have similar purpose have very different syntax (case vs. select)

·         Constructs that have similar syntax have very different semantics (variables vs signals)

·         Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)

VHDL Advantages

·         VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.

·         VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.

·         VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.

·         VHDL has a rich collection of datatypes

·         VHDL is a full-featured language with a good module system (libraries and packages).

·         VHDL has a well-defined standard.

VHDL and Other Languages

·         VHDL vs Verilog

o    Verilog is a "simpler" language: smaller language, simple circuits are easier to write

o    VHDL has more features than Verilog

§  richer set of data types and strong type checking

§  VHDL offers more flexibility and expressivity for constructing large systems.

o    The VHDL Standard is more standard than the Verilog Standard

§  VHDL and Verilog have simulation-based semantics

§  Simulation vendors generally conform to VHDL standard

§  Some Verilog constructs don't simulate the same in different tools

o    VHDL is used more than Verilog in Europe and Japan

o    Verilog is used more than VHDL in North America

o    South-East Asia, India, South America - More Democratic

·         VHDL vs SystemC

o    System C looks like C —familiar syntax

o    C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?

o    If you think VHDL is hard to synthesize, try C....

o    SystemC simulation is slower than advertised

·         VHDL vs Other Hardware Description Languages

o    Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.

o    SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.

o    Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.

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